1. Field of the Invention
The present invention relates to a method for fabricating a memory device and, more particularly, to a method fabricating a nonvolatile memory device such as electrically erasable programmable ROM (EEPROM).
2. Background of the Related Art
With the development of high-capacity memory devices, nonvolatile memory devices are being increasingly important. An example of the nonvolatile memory device is EEPROM.
In the EEPROM, a tunneling region is formed under a floating gate region. Here, the tunneling region has to be narrower than the floating gate region in order to ensure high coupling ratio. The tunneling region is defined as a tunnel window. The tunnel window is one of most important parts in a nonvolatile memory device. The memory device operates by movement of electrons through the tunnel window.
FIG. 1 illustrates, in a cross-sectional view, a structure comprising an oxide pattern 10 and a gate poly pattern 14 on a substrate 10. Here, “L1” indicates a tunnel window. FIG. 2 is a graph illustrating relation between the width of tunnel window and the coupling ratio in a nonvolatile memory device. The coupling ratio increases as the width of the tunnel window becomes narrower. Therefore, present technology now focuses on the development of the process for forming a narrow tunnel window.
FIGS. 3a and 3b illustrate, in cross-sectional views, the fabricating process of a nonvolatile memory device according to a conventional method.
Referring to FIG. 3a, an oxide layer 32 is formed on a substrate 30 and a photoresist pattern 34 is formed on the oxide layer 32. Referring to FIG. 3b, some part of the oxide layer 32 is removed by an etching process using the photoresist pattern 34 as a mask to form an oxide pattern 32a. The etching process is generally wet etching and, therefore, the oxide pattern 32a is etched isotropically. As a result, linewidth of the region etched in the oxide pattern 32a is broader than the linewidth defined by the photoresist pattern. Such broadened linewidth results in low coupling ratio, thereby causing deterioration of device characteristics.
In manufacturing a semiconductor device, a lot of methods for shrinking critical dimension of any structure have been proposed. Among them, U.S. Pat. No. 6,579,808, Cho et al., discloses a method for fabricating a semiconductor device capable of maintaining contact hole of fine size when the contact hole for bit line formation is defined. The disclosed method by the Cho et al. patent comprises forming an insulating layer and an ARC (anti-reflective coating) layer on a substrate; removing some part of the ARC layer through a first dry etching process using a photoresist pattern as a mask and, at the same time, attaching polymers resulting from the dry etching process to the remaining ARC layer to form a polymer sidewall; and removing some part of the insulating layer through a second dry etching process using the photoresist pattern and the polymer sidewall as a mask to form a contact hole.
As another example, U.S. Pat. No. 6,368,974, Tsai et al., proposes a method for shrinking equivalent critical dimension of mask by in situ polymer deposition and etching. In the method by Tsai et al. patent, a polymer layer is formed on a photoresist layer and etched by a plasma reactor with at least two independent power sources. Here, voltages of all power source are adjusted such that etching rate and depositing rate are equivalent on surface of the photoresist layer and etching rate is larger than depositing rate in bottom of any structure of the photoresist layer. Therefore, the sidewall of any structure is filled by a conformal polymer layer and, then, width of any structure is efficiently decreased. Accordingly, the critical dimension of any structure is significantly smaller than critical dimension of the mask.
As another example, U.S. Pat. No. 6,319,822, Chen et al., discloses a method for etching of sub-quarter micron openings in insulating layers for contacts and via. The method by Chen et al. patent uses a hardmask formed of carbon enriched titanium nitride. The carbon is released as the hardmask erodes during plasma etching and participates in the formation of a protective polymer coating along sidewalls of the opening etched in the insulating layer. The protective sidewall polymer inhibits lateral chemical etching.